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may 2012 doc id 023131 rev 1 1/13 AN4104 application note using the stm32f0xx dma controller introduction this application note describes how to use the stm32f0xx direct memory access (dma) controller. the stm32f0xx dma controller, the cortex?-m0 core, the advanced microcontroller bus architecture (amba) bus and the memory system contribute to provide a high data bandwidth and to develop very-low latency response time software. this application note also describes how to take full advantage of these features and ensure correct response times for diff erent peripherals and subsystems. note: to ensure a quick start, application cases presented in this document are implemented in c language and are available in project\stm32f0xx_stdperiph_examples within the stm32f0xx_stdperiph_lib package. www.st.com
contents AN4104 2/13 doc id 023131 rev 1 contents 1 dma controller description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 dma overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 dma data managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.1 round robin priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 peripheral to memory, memory to peripheral and peripheral to peripheral dma transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.3 memory to memory dma transactions . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.4 choosing channel priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 dma interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 dma firmware driver api . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 how to use dma driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 dma programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 adc dma transfer to tim example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 dma flash to ram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 dma ram to dac example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 spi dma example: communication between two spis using dma . . . . . 11 3.5 usart communication boards data exchange using dma example . . . 11 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AN4104 dma controller description doc id 023131 rev 1 3/13 1 dma controller description direct memory access (dma) is used in order to provide high-speed data transfer betweenperipherals and memory as well as memory to memory. data can be quickly moved by dma without any cpu actions. this keeps cpu resources free for other operations. the dma allows data transfers to take place in the background, without the intervention of the cortex-m0 processor. during this operation, the main processor can execute other tasks and it is only interrupted when a whole data bl ock is available for processing. large amounts of data can be transferred with no major impact on the system performance. the dma is mainly used to implement central data buffer storage (usually in system sram) for different peripheral modules. this solution is less expensive in terms of silicon and power consumption compared to a distributed solution where each peripheral needs to implement its own local data storage. depending on the sales type used, one or two dma controllers are implemented . the stm32f0xx dma controller has 5 channels for dma1 in total, each dedicated to manage memory access requests from one or more peripherals. it has an arbiter for handling the priority between dma requests. 1.1 dma overview the dma(s) offer(s): independently configurable channels (requests) each channels are connected to dedicated hardware dma requests, software trigger is also supported on each channel priorities between requests from channels of one dma are software programmable (4 levels: very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. the source and the address must have the same data size (to be aligned on the data size). support for circular buffer management 3 event flags (dma half transfer, dma transfer complete and dma transfer error) logically ored together in a single interrupt request for each channel memory-to-memory transfer peripheral-to-memory and memory-to-peripheral as well as peripheral-to-peripheral transfers access to flash, sram, apb and ahb peripherals as source and destination programmable number of data to be transferred: up to 65536 the dma aims to offer a relatively large data buffer to all peripherals. this buffer is usually located in system sram. each channel is assigned to a unique peripheral (data channel) at a given time. peripherals connected to the same dma channel (ch1 to ch5 in ta b l e 1 for stm32f0xx devices) cannot be used simultaneously with active dma (dma function active in the peripheral register).
dma controller description AN4104 4/13 doc id 023131 rev 1 the different peripherals supporting dma transfers in stm32f0xx devices are shown in ta bl e 1 . note: for more details,refer to rm0091 dma section for stm32f0xx devices. 1.2 dma data managing the dma controller performs direct memory transfer by sharing the system bus with the cortex-m0 core. when the cpu and dma are targeting the same destination (memory or peripheral) the dma request may stop the cpu access to the system bus for several bus cycles. the bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the cpu. table 1. peripherals served by dma1 and channel allocation peripherals ch1 ch2 ch3 ch4 ch5 adc adc1 adc1 adc1 spi spi1 spi1_rx spi1_tx spi2 spi2_rx spi2_tx usart usart1 usart1_ tx usart1_rx usart1_ tx usart1_rx usart2 usart2_ tx usart2_rx i 2 c i 2 c1 i2c1_tx i2c1_rx i 2 c2 i2c2_tx i2c2_rx tim tim1 tim1_ch1 tim1_ch2 tim1_ch4 tim1_trig tim1_com tim1_up tim1_ch3 tim2 tim2_ch3 tim2_up tim2_ch2 tim2_ch4 tim2_ch1 tim3 tim3_ch3 tim3_ch4 tim3_up tim3_ch1 tim3_trig tim6/dac tim6_up dac tim15 tim15_ch1 tim15_up tim15_trig tim15_com tim16 tim16_ch1 tim16_up tim16_ch1 tim16_up tim17 tim17_ch1 tim17_up tim17_ch1 tim17_up
AN4104 dma controller description doc id 023131 rev 1 5/13 1.2.1 round robin priority scheme the nvic and cortex-m0 processor implement a high-performance very low latency interrupt scheme. all cortex-m0 instructions are either executed in a single cycle or are interruptible at cycle level. in order to preserve this advantage at system level, the dma and bus matrix ensure that the dma does not block the bus for a long time. the round-robin priority scheme ensures that the cpu can access any slave buses during every second cycle, if needed. 1.2.2 peripheral to memory, memory to peripheral a nd peripheral to peripheral dma transactions after an event, the peripheral sends a request signal to the dma controller. the dma controller serves the request depending on the channel priorities. as soon as the dma controller accesses the peripheral, an acknowledge is sent to the peripheral by the dma controller. the peripheral releases its request as soon as it gets the acknowledge from the dma controller. once the request is deasserted by the peripheral, the dma controller releases the acknowledge. if there are more requests, the peripheral can initiate the next transaction. each dma transfer consists of three operations: the loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. the start address used for the first transfer is the base peripheral/memory address. the storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. the start address used for the first transfer is the base peripheral/memory address. the post-decrementing of the dma counter, which contains the number of transactions that still have to be performed. 1.2.3 memory to memory dma transactions the dma channels can also work without being triggered by a request from a peripheral. this mode is called memory to memory mode. if the mem2mem bit is set, then the channel initiates transfers as soon as it is enabled by software by setting the enable bit. the transfer stops once the dma counter reaches zero. memory to memory mode may not be used at the same time as circular mode. 1.2.4 choosing channel priority in order to achieve continuous data transfers to/from a peripheral, the corresponding dma channel must be able to sustain the peripheral data rate and ensure that the service latency is shorter than the period of time between two consecutive data. the high speed/high bandwidth peripherals must have the highest dma priorities. this ensures that the maximum da ta latency will be respected for these peripherals and over/under-run condi tions will be avoided. in case of equal bandwidth requirements, it is recommended to assign a higher priority to the peripherals working in slave mode (which have no control on the data transfer speed) compared with the ones working in master mode (which may control the data flow).
dma controller description AN4104 6/13 doc id 023131 rev 1 by default, the channel allocation and hardware priority (from 1 to 5 for stm32f0xx devices) are set in order to assign the fastest peripherals to the highest priority channels. however, this may not be true for some applications. in this case, the user can configure a software priority for each channel (4 levels ? from very high to low), which takes precedence over the hardware priority. 1.3 dma interrupt management an interrupt can be produced on a half-transfer, transfer complete or transfer error for each dma channel. separate interrupt enable bits are available for flexibility. when a dma transfer error occurs during a dma read or a write access, the faulty channel is automatically disabled through a hardware clear of its enable bit in the corresponding channel configuration register (dma_ccrx). the channel's transfer error interrupt flag (teif) in the dma_ifr register is set and an interrupt is generated if the transfer error interrupt enable bit (teie) in the dma_ccrx register is set. table 2. dma interrupt requests interrupt events event flags control bit enable half transfer htif htif transfer complete tcif tcif transfer error teif teif
AN4104 dma firmware driver api doc id 023131 rev 1 7/13 2 dma firmware driver api this driver provides a set of firmware functions to manage the following functionalities of the dma peripheral: ? initialization and configuration functions ? data counter functions ? interrupts and flags management functions for the stm32f0xx family, the dma driver stm32f0xx_dma.c/.h can be found in the directory: stm32f0xx_stdperiph_lib_vx.y.z\libraries\stm32f0xx_stdperiph_driver. this driver provides a fully compatible api making it easy to move from one product to another. several parameters such as source/destination address (location where data is to be read or transferred) and transfer length must be specified in order for a dma transaction to take place. table 3. dma functions description groups function name description initialization and configuration functions dma_deinit deinitializes the dmay channelx registers to their default reset values. dma_init initializes the dmay channelx according to the specified parameters in the dma_initstruct. dma_structinit fills each dma_initstruct member with its default value. dma_cmd enables or disables the specified dmay channelx. data counter functions dma_setcurrdatacounter sets the number of data units in the current dmay channelx transfer. dma_getcurrdatacounter returns the number of remaining data units in the current dmay channelx transfer. interrupts and flags management functions dma_itconfig enables or disables the specified dmay channelx interrupts. dma_getflagstatus checks whether the specified dmay channelx flag is set or not.. dma_clearflag clears the dmay channelx's pending flags. dma_getitstatus checks whether the specified dmay channelx interrupt has occurred or not. dma_clearitpendingbit clears the dmay channelx's interrupt pending bit..
dma firmware driver api AN4104 8/13 doc id 023131 rev 1 the dma field configuration is stored in a structure as described below: ? dma_peripheralbaseaddr : specifies the peripheral base address for dmay channelx. ? dma_memorybaseaddr : specifies the memory base address for dmay channelx. ? dma_dir : specifies if the peripheral is the source or destination. ? dma_buffersize : specifies the buffer size, in data unit, of the specified channel. the data unit is equal to the configuration set in dma_peripheraldatasize or dma_memorydatasize members depending in the transfer direction. ? dma_peripheralinc : specifies whether the peripheral address register is incremented or not after transferring each unit. ? dma_memoryinc : specifies whether the memory address register is incremented or not after transferring each unit. ? dma_peripheraldatasize : specifies the peripheral data width. the size of the transfer unit can be byte, half-word or word. ? dma_memorydatasize : specifies the memory data width. the size of the transfer unit can be byte, half-word or word. ? dma_mode : specifies the operation mode of the dmay channelx (normal or circular mode). ? dma_priority : specifies the software priority for the dmay channelx. ? dma_m2m : specifies if the dmay channelx will be used in memory-to-memory transfer. note: for further details, please refer to the dma section in the reference manual rm0091 for stm32f0x devices.
AN4104 dma firmware driver api doc id 023131 rev 1 9/13 2.1 how to use dma driver 1. before using the dma driver, enable the dma controller clock using rcc_ahbperiphclockcmd (rcc_ahbperiph_dmax, enable) function. 2. enable and configure the peripheral to be connected to the dma channel (except for internal sram / flash memories: no initialization is necessary). 3. for a given channel, program the source and destination addresses, the transfer direction, the buffer size, the peripheral and memory incrementation mode and data size, the circular or normal mode, the channel transfer priority and the memory-to- memory transfer mode (if needed) using the dma_init() function. 4. enable the nvic and the corresponding interrupt(s) using the function dma_itconfig() if you need to use dma interrupts. 5. enable the dma channel using the dma_cmd() function. 6. activate the needed chan nel request using ppp_dmacmd() function for the adequate ppp peripheral except internal sram and flash (ie. spi, usart...) the function allowing this operation is provided in each ppp peripheral driver (ie. spi_dmacmd for spi peripheral). 7. optionally, configure the number of data to be transferred when the channel is disabled (ie. after each transfer complete event or when a transfer error occurs) using the function dma_setcurrdatacounter(). and you can get the number of remaining data to be transferred using the function dma_getcurrdatacounter() at run time (when the dma channel is enabled and running). 8. to control dma events you can use one of the following two methods: ? check on dma channel flags using the function dma_getflagstatus(). ? use dma interrupts through the function dma_itconfig() at initialization phase and dma_getitstatus() function into interrupt routines in communication phase. after checking on a flag, clear it using dma_clearflag() function. and after checking on an interrupt event, clear it using dma_clearitpendingbit() function.
dma programming examples AN4104 10/13 doc id 023131 rev 1 3 dma programming examples the dma firmware driver is provided with a set of examples, so you can quickly become familiar with the dma peripheral. it demonstrates how to use the dma in different modes. both the package and the application note are available for download from the stmicroelectronics website: http://www.st.com. 3.1 adc dma transfer to tim example this example provides a description of how to use a dma channel to transfer continuously a data from a peripheral (adc) to another peripheral (tim) supporting dma transfer. the adc is configured to operate in continuous conversion mode. tim is configured to generate a pwm signal on its output. the dedicated dma channel is configured to transfer in circular mode the last adc channel converted value to the timer capture/compare register. the dma channel request is driven by the tim update event. the duty cycle of timer channel output signal is then changed each time the input voltage value on adc channel pin is modified. the duty cycle variation can be visualized on oscilloscope wh ile changing the analog input on adc channel using the potentiometer. 3.2 dma flash to ram example this example illustrates how to use the dm a to transfer data between two memory locations. it provides a description of how to transfer a word data buffer located in flash memory to embedded sram memory using dma channel. dma channel is configured to transfer the contents of a 32-word data buffer stored in flash memory to the reception buffer declared in ram. the start of transfer is triggered by software. dma channel memory-to-memory transfer is enabled. source and destination addresses incrementing is also enabled. the transfer is started by setting the channel enable bit for dma channel. at the end of the transfer, a transfer complete interrupt is generated since it is enabled. once interrupt is generated, the remaining data to be transferred is read which must be equal to 0 (dma counter reaches 0 if all data are transferred). the transfer complete interrupt pending bit is then cleared. a comparison between the source and destination buffers is done to check that all data have been correctly transferred. 3.3 dma ram to dac example this example provides a description of how to use a dma channel to transfer data buffer from memory (ram memory) to the peripheral dac. the dma channel is configured to transfer continuously, word by word, a half-word buffer from the ram memory to the dac register dac_dhr12r. the dac channel conversion is
AN4104 dma programming examples doc id 023131 rev 1 11/13 configured to be triggered by tim2 trgo triggers and without noise/triangle wave generation. 12bit right data alignment is sele cted since we choose to access dac_dhr12r register. 3.4 spi dma example: communic ation between two spis using dma this example provides an spi communications using dma. in master board, the spi peripheral is configured as master full duplex with dma and nss hardware mode. the tim2 is configured to generate 4 khz pwm signal with 50% duty cycle on tim2_ch2 pin (pa.01), this signal is used as dma trigge r and as nss signal input to latch the spi data transfers. whereas in slave board, the spi peripheral is configured as slave full duplex with dma and nss hardware mode. the master sends the specific command to the slave using the tim2_ch2 dma request (dma1_channel3) (the command contains the transaction code (cmd_right, cmd_left, cmd_up, cmd_do wn or cmd_sel) and receives the ack command from the slave using spi_rx dma request (dma1_channel2). the slave receives the command using spi_rx dma request (dma1_channel2) and sends the ack command using the spi_tx dma request (dma1_channel3). 3.5 usart communication boards data exchange using dma example this example provides a small application of usart communications using dma. in both boards, the data transfers is managed using the usart tx/rx channels dma requests.
revision history AN4104 12/13 doc id 023131 rev 1 4 revision history table 4. document revision history date revision changes 02-may-2012 1 initial release
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